1. Field of the Invention
This invention relates to semiconductor logic arrays, and more particularly to gate-array cell layouts for flip-flops with set and clear.
2. Description of the Related Art
Higher densities of integration of semiconductor circuits have yielded a dramatic reduction in electronic component cost. Semi-custom chips reduce the initial tooling costs for new circuits (the non-recurring engineering or NRE costs). Semi-custom chips reduce tooling costs by customizing relatively few masking layers while using standard layouts for other masking layers. For example, gate-array semi-custom chips have an array of transistors formed in a standard layout in the base masking layers, such as the active-area, implant, polysilicon layers. Upper masking layers, such as contacts, metals, and vias are customized for each customer's circuit design.
While such gate-array chips are effective at reducing costs, often the transistors are arrayed less compactly than custom circuits. The larger area required increases production costs for a gate-array implementation of a circuit compared to a custom implementation of the circuit. A more efficient, compact gate-array cell is thus desirable.